Stable high voltage semiconductor device structure

ABSTRACT

A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exist between each of such guard rings. At least one field plate couples to a main junction region, and another field plate couples to a peripheral region, typically a scribe line. The present power device structure with multiple guard rings and field plates provides a resulting guard ring structure which allows for such device to achieve higher voltage applications.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to integrated circuit devices, andin particular high voltage semiconductor switching devices such as highvoltage transistors, power MOSFETs, power IGBTs, thyristors, MCTs, andthe like (hereinafter called power devices).

[0002] Conventional power devices are fabricated by conventionalsemiconductor processing techniques on a single crystallinesemiconductor substrate such as a silicon wafer. Conventionalsemiconductor processing techniques include doping and implanting,lithography, diffusion, chemical vapor deposition (CVD), wet and dryetching, sputtering, epitaxy, oxidizing, among others. A complexsequence of these processing techniques is often required to produce isa high voltage device having a breakdown voltage within the 30 to 1200volt range.

[0003] A limitation with the conventional power device is its shallowjunction region. The shallow junction region often creates low junctioncurvature and reduces the breakdown voltage of the device. This lowerbreakdown voltage is often an undesirable result for high voltageapplications.

[0004] Industry has proposed or even attempted to overcome suchlimitation with use of a guard ring formed adjacent to the main junctionof the power device. The guard ring typically provides a junctiontermination technique for the convention power device. A conventionalguard ring is often formed by selectively placing certain dopants aroundthe periphery of the main junction, typically in a “race track” or“ring” type pattern. The dopants often include impurities of the sameimpurity type as the main junction. Ideally, the guard ring keeps themain junction in its place.

[0005] However, as industry demands for power devices with even higherbreakdown voltages and even smaller device features, the presence ofcontamination on certain portions of a convention guard ring structuredetrimentally effects an electric field therein, thereby degrading thebreakdown voltage of the device. Accordingly, the presence ofcontamination often creates a resulting power device that is unstable,unreliable, or the like.

[0006] Another technique often used to preserve the breakdown voltage ofthe device is to form a field plate located between certain guard ringsfor the purpose of reducing electric fields thereby. The field plate isformed overlying an oxide layer, also located overlying regions betweenthe guard rings. Ideally, lower electric fields at such location shouldtend to increase the breakdown voltage of the device. However, alimitation with the field plate structure often occurs with powerdevices having higher breakdown voltages.

[0007] For example, power devices with even higher breakdown voltagesproduce an even higher electric field underneath portions of the oxidelayer. The higher electric field generally promotes certain hot electroneffects such as electrons being injected and trapped into portions ofthe oxide layer, and the like. As charge builds up in the oxide layerfrom the trapped electrons, the conventional device often experiencesdetrimental effects such as current leakage, voltage instability,unreliability, and the like.

[0008] From the above, it is seen that a method and structure forproviding a device with a high breakdown voltage that is easy tomanufacture, reliable, and cost effective is often desired.

SUMMARY OF THE INVENTION

[0009] The present invention provides an power integrated circuit devicewith a combination of multiple guard rings and field plates for thepurpose of achieving high voltage applications. Benefits of the presentinvention are achieved in the context of known technology.

[0010] The present invention provides a power device that includes asemiconductor substrate having a top surface with an active region, aguard ring region, and a peripheral region. The active region includes ajunction region. The present power device also includes a plurality ofguard rings formed onto the semiconductor substrate in the guard ringregion, typically located between the active region and the peripheralregion. The plurality of guard rings has a first guard ring nearest tothe junction region and a last guard ring nearest to the peripheralregion. The present power device further has a dielectric layeroverlying the top surface and having portions between each of theplurality of guard rings. The dielectric layer also includes a portionbetween the junction region and the first guard ring, and anotherportion between the last guard ring and the peripheral region. A fieldplate layer is also provided. The field plate layer is overlying each ofthe dielectric layer portions between each of the plurality of guardrings. The field plate layer is also overlying the dielectric layerportion between the junction region and the first guard ring. The fieldplate layer further overlies the dielectric layer portion between thelast guard ring and the peripheral region.

[0011] In an alternative embodiment, the present invention provides apower device with a semiconductor substrate that includes a top surfacewith an active region, a guard ring region, and a peripheral region. Theactive region includes a junction region. The present power device alsoincludes a plurality of guard rings formed onto the semiconductorsubstrate in the guard ring region. The guard ring region is locatedbetween the active region and the peripheral region. The plurality ofguard rings includes at least a first guard ring nearest to the junctionregion and a last guard ring nearest to the peripheral region. Adielectric layer overlying the top surface and having portions betweeneach of the plurality of guard rings is also provided. The dielectriclayer also has a portion between the junction region and the first guardring. A dielectric layer portion between the last guard ring and theperipheral region is further provided. The present power device includesa field plate layer. The field plate layer has a plurality of fieldplates overlying each of the dielectric layer portions between each ofthe plurality of guard rings, and a field plate located between thejunction region and the first guard ring. The field plate layer alsoincludes a plurality of field plates overlying the dielectric layerportion between the last guard ring and the peripheral region.

[0012] In a further alternative embodiment, the present inventionprovides a method of forming a guard ring structure. The present methodincludes providing a partially completed semiconductor device with anactive region, guard ring region, and peripheral region. The activeregion includes a junction region, and the guard ring region existsbetween the active region and the peripheral region. The guard ringregion also has a plurality of diffusion region. The present method alsoincludes steps of forming a dielectric layer overlying the partiallycompleted semiconductor substrate, and forming a field plate layeroverlying the dielectric layer. A step of defining the dielectric layerand field plate layer to form a plurality of openings over the diffusionregions is also provided. The dielectric layer and field plate layer isalso defined to expose the junction region and the peripheral region.The present method further has a step of providing implants into theopenings to define a plurality of guard rings. The plurality of guardrings includes at least a first guard ring proximate to the junctionregion and a last guard ring proximate to the peripheral region.

[0013] A further understanding of the nature and advantages of thepresent invention may be realized by reference to the latter portions ofthe specification and attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a simplified cross-sectional view of a portion of aconventional power device;

[0015]FIG. 1A is an enlarged cross-sectional view of a portion of thedevice of FIG. 1;

[0016]FIGS. 2 and 3 illustrate typical current and voltage diagrams forconventional power devices;

[0017]FIG. 4 is a simplified cross-sectional view of an embodiment of aguard ring structure according to the present invention;

[0018] FIGS. 5-8 illustrate a simplified fabrication method for theguard ring structure of FIG. 4;

[0019]FIG. 9 is a simplified cross-sectional view of an alternativeembodiment of a guard ring structure according to the present invention;

[0020]FIG. 10 is a simplified cross-sectional view of a furtheralternative embodiment of a guard ring structure according to thepresent invention;

[0021]FIG. 11 is a simplified top-view diagram of still a furtherembodiment of guard ring structure according to the present invention;and

[0022]FIG. 12 is a simplified cross-sectional view of an alternativeembodiment of the present invention.

DESCRIPTION OF THE SPECIFIC EMBODIMENT

[0023] Prior Art Guard Ring Structures

[0024]FIG. 1 is a simplified cross-sectional view of a prior art guardring structure 10 for a conventional power device. The conventionalpower device includes an N− type epitaxial layer 12 formed on an N+ typesemiconductor substrate 14. The guard ring structure may have certain Ptype regions defined in the N− type epitaxial layer 12. Typically the Ptype regions include a main blocking region 16, multiple guard rings 18,20, and 22, and a scribe region 24. A field oxide layer is often definedoverlying regions between each of the aforementioned P type regions. Thefield oxide layer includes oxide regions 26, 27, 28, and 30. The guardring structure also includes a field layer defined by field plate 32,34, 36, 38, and 40 formed over each of the field oxide regions. A metallayer used as contacts are also formed overlying portions of certainguard rings and portions of certain field plates. The metal layerincludes metal contacts 46, 48, 50, 52, and 54. An exposed annular oxideregion 44 is defined between field plate 38 and 40, typically isolatingsuch structures to provide a high voltage difference therebetween.

[0025] The guard ring structure is designed to reduce the electric fieldof the main junction region and thereby provide for a higher breakdownvoltage. This often occurs by providing a higher junction curvature.Otherwise, a low junction curvature caused by a shallow junction mayreduce the breakdown voltage of the device. Ideally, the highest voltagepotential in a conventional device exists at the backside of the N+substrate and the scribe region 54, typically a front surface portion ofthe N+ substrate. The lowest voltage potential exists at the main P typejunction 17, and such voltage potential increases from such mainjunction in the N− region to an edge of the die, typically the scriberegion for an N channel device.

[0026] The voltage potential at each guard ring for a given appliedreverse voltage is typically based at least upon the distance betweeneach guard ring and the main P type junction. For example, guard ringsfurther from the main junction often have a higher voltage potential andtherefore a higher applied reverse voltage than guard rings closer tothe main P type junction. In such example, a depletion region spreadsfrom the main P type junction 16 to outer N− type regions of the die.

[0027] However, the annular oxide region 44 is often exposed and subjectto contamination from particles, ionic species, and others that may comein contact with such region. Typically the presence of contaminationoccurs with the use of non-hermetically sealed packages such as plasticmolded packages, modules, hybrids, bare dice on substrates, and others.The contamination often modifies an electric field in the semiconductorunder such annular oxide region 44, typically at region 56, and thuschanges the breakdown voltage of the device to create problems such asunreliability, instability, among others.

[0028] Another limitation with the prior art device of FIG. 1 may beillustrated by FIG. 1A, an enlarged cross-sectional view of a portion ofthe device of FIG. 1. The same reference numerals are used for easycross-reference. As shown, field plate 36 connects to guard ring 20through metal contact 50. Accordingly, about the same voltage potentialexists at both field plate 36 and guard ring 20. As discussed, guardring 22 includes a higher voltage potential than guard ring 20 and soon. This means the voltage potential at the N− type region 58 can bemuch higher than the voltage potential at guard ring 20, but slightlylower than the voltage potential at guard ring 22. Since field plate 36has about the same voltage potential as guard ring 20, a higher voltagedrop develops at the field oxide region 28 between such field plate 36and guard ring 22. In addition, a higher voltage drop also develops atthe field oxide region 28 between such field plate 36 and N− type region58.

[0029] The higher voltage drop from the field plate 36 contributes anelectric field component in the N− type region 58, in addition to thefield created by the given reverse voltage applied to such device. Theelectric fields create hot electron effects such as the injection andtrapping of hot electrons into the field oxide 28, typically near theguard ring 22. Accordingly, the higher voltage drop generally leads toan increase charge build up at the oxide region 28, often contributingleakage currents that drift up with time while the device is underreverse bias. Such leakage currents may create problems such as apparentinstability, long term device degradation, device damage, and others.

[0030] A further limitation typically occurs when the distance betweenguard rings 20 and 22 effectively increases. This increases the electricfield of certain portions of the device beyond the critical “avalanchefield.” In such instance, localized device breakdown can occur at lowerthan normal applied voltage values, often creating problems such asdevice failure, destruction, and others.

[0031]FIGS. 2 and 3 illustrate current and voltage diagrams ofconventional power devices as compared to an ideal power device. Theconventional power device may be a high voltage MOSFET, IGBT, or othersemiconductor switching devices. The conventional power device includescertain guard rings and field plates. As shown, current leakageincreases with time due to the higher voltage drop between the fieldplate and underlying semiconductor (also known as field concentrationeffects) illustrated by FIG. 2. For t>0, the current fluctuates withrespect to voltage. For example, each of the current/voltage plots att₁, and t₂ illustrate fluctuating values of voltage with respect tocurrent. FIG. 3 illustrates the effects of surface contamination in theoxide of the annular region. For t>0 and a given reverse voltage, the“leakage” current across the device increases, which is a typical signof degradation. Ideally, in both of the FIGS., the current should followthe current/voltage path represented at time=0 (t=0).

[0032] Present Guard Ring Structures

[0033]FIG. 4 is a simplified cross-sectional view of an embodiment 100of a guard ring structure according to the present invention. Thisembodiment uses P type main junction regions and guard rings formed ontoan N+ type substrate for illustrative purposes only. It will berecognized that such an embodiment may also be formed with use of N typemain junction regions and guard rings, and others. The guard ringstructure includes P type regions 102, 103, 105, 106, 108, 109, andothers formed on an N− type epitaxial layer 110. The N− type epitaxiallayer is defined on an N+ type substrate 112. P type regions 102, 103,105, and 106 each define guard rings. As for P type region 109, ittypically defines a portion of a scribe line. An insulting layer formsinsulating regions 115, 117, 119, 121, 123, and others. A field platelayer forms fixed field plate regions 125, 27, 131, 133, 135, 137, andothers. Floating field plate regions 141, 143, 145, 147, 149, and 151are defined from the field plate layer. The guard ring structure alsoincludes a metallization layer that forms contacts 153, 155, 157, 159,161, 163, among others.

[0034] The N type substrate can be any suitable substrate for use withhigh voltage applications. The N type substrate is often a neutrontransmuted substrate, epitaxial, or any substrate capable of achievinghigh voltage applications. The substrate is often composed of one ormore layers of different doping types or dopant concentrations. “EPI”substrates (i.e., epitaxial), as an example, are composed of an N+substrate onto which more layers at different dopants and concentrationsare grown. Typically the substrate includes a thickness ranging fromabout 0.1 mm to about 0.7 mm, depending on the wafer diameter andapplication, and preferably at about 0.5 mm for a 125 mm diameter wafer.The impurity concentration of such substrate is varied, according to thespecific layer. The N+ region is typically of 10¹⁷ atoms/cm³ of silicon,while the N− layer might be typically at 10¹³−10¹⁴ atoms/per cm³silicon. Of course, the concentration and thickness of such substratedepends upon the particular application.

[0035] P type regions defined in the N− type layer typically form by wayof masking, implantation, diffusion, and the like. Preferably, the Ptype regions are P+/P− type regions. Each of the P type regions 102,103, 105, 106, 108, and others define a guard ring or the like. Adistance ranging from about 3 μm to about 100 μm. The guard ring spacingdepends on the ring number and the desired voltage rating. For highvoltage applications, the distance between each guard ring is 3-10 μm onthe average, and preferably in an increasing sequence from first to lastring. The distance between each of the guard rings may be a constant,increasing, decreasing, combinations thereof, or the like. Each guardring may be floating, that is, not specifically connected to any otherwell structure. Of course, the configuration of each P type regiondepends upon the particular application.

[0036] The dielectric layer overlying regions between each of the guardrings include materials such as silicon dioxide, silicon nitride,combinations thereof, and the like. Preferably, silicon dioxide is usedat a thickness ranging from about 0.04 μm to about 2.5 μm, andpreferably about 0.1 μm to about 1.5 μm.

[0037] Field plates include fixed field plates 125, 127, 131, 133, 135,137, and others, and floating field plates 141, 143, 145, 147, 149, and151. The connected field plates connect to an adjacent guard ring by wayof contact metalization. For example, field plate 125 couples to guardring 102 by use of contact 153, field plate 127 couples to guard ring103 by use of contact 155, field plate 131 couples to guard ring 105 byuse of contact 157, field plate 133 couples to guard ring 106 by use ofcontact 159, and so on. The other field plates 141, 143, 145, 147, 149,151, and others are typically called floating field plates, that is,each of such field plates do not couple to a guard ring. The fieldplates can be made from any suitable metal material, polysilicon,suicides, combinations thereof, and the like. The field plate may alsobe doped or undoped, depending upon the application. The distanceseparating field plates on each insulating region ranges from about 25μm to about 1 μm or less.

[0038] The series of field plates 135, 149, 151, and 137 located at anouter periphery 170 of the semiconductor preferably has at least twofield plates coupled to certain portions of the semiconductor. As noted,field plate 135 couples to guard ring 108 by use of contact 161. Fieldplates 149 and 151 are floating, and field plate 137 couples to p typeregion 109, often defining the scribe region. Preferably, the distancebetween each such field plates is no greater than about 4 μm, the widthof each of such field plates ranges from about 32 μm to about 2 μm orless. The configuration of field plates in region 170 provides for amore uniform distribution of electric fields in region 172, therebyproviding for higher voltage applications.

[0039] The presence of multiple field plates in the aforementionedconfiguration provides a guard ring structure that reduces the electricfield underlying certain portions of the dielectric regions. The reducedelectric field preserves the breakdown voltage of the present powerdevice structure. By way of this configuration, breakdown voltagesranging from about 50 volts to about5000 volts may be achieved.

[0040] In an alternative embodiment, FIGS. 5-8 illustrate a simplifiedfabrication method for the guard ring structure of FIG. 4. Thefabrication method begins by providing a silicon substrate, preferablyan N+ type silicon substrate, and more preferably an neutron transmutedN+ type silicon substrate. After conventional polishing and cleaningroutines, an N+ type epitaxial is defined onto a top surface of the N+type silicon substrate. FIG. 5 illustrates a simplified cross-sectionalview of a N+ type silicon substrate 112 and an N− type epitaxial layer110.

[0041] An implant step forms P type well regions, guard ring regions,and others onto the N− type epitaxial layer. Typically the surface ofsuch N− type epitaxial layer is oxidized, masked, and implanted to formP type well regions and P type guard ring regions 102, 103, 105, 106,and 108. A step of diffusion may be subsequent to the implant step todiffuse the P type impurities, typically boron or the like. Theconcentration of the P type impurities ranges from about 10¹⁴ atoms/cm³to about 10¹⁸ atoms/cm³, and preferably at about 10¹⁷ atoms/cm³. An Ntype implant is then often performed at channel regions of for example apower MOSFET device. Of course, the particular concentration useddepends upon the particular application.

[0042] A dielectric layer 111 of one or more thicknesses also known as agate dielectric layer, preferably silicon dioxide, is then formedoverlying the top surface of the structure of FIG. 5 as illustrated byFIG. 6. A silicon dioxide layer has a thickness ranging from about 0.05μm to about 2.5 μm, and preferably at about 1.5 μm. The dielectric layercan be in steps under the field plate, of various step height as shownin FIG. 12. A field plate layer 113 such as a polysilicon layer or thelike is defined overlying the oxide layer. The polysilicon layerincludes a thickness ranging from about 0.3 μm to about 1 μm, andpreferably at about 0.5 μm. The polysilicon layer is also doped with Ntype dopants such as phosphorous or the like at a concentration rangingfrom about 10¹⁵ atoms/cm³ to about 10¹⁹ atoms/cm³, and preferably atabout 10₁₆ atoms/cm³. Of course, the particular thicknesses andconcentrations used depend upon the application.

[0043] A masking step defines the field plate layer to form each of thefixed field plates 125, 127, 131, 133, 135, and 137, and floating fieldplates 141, 143, 145, 147, 149, and 151. Another masking step defineseach of the openings over the P type guard rings 102, 103, 105, 106, and108. P+ type dopants may be implanted and diffused into each of the Ptype guard ring regions through the openings.

[0044] Contacts are formed on field plates 125, 127, 131, 133, 135, and137 as illustrated by FIG. 8. Each of these contacts form overlying itsrespective P type guard ring 102, 103, 105, 106, and 108, and is alsocoupled to a top surface of a respective field plate 125, 127, 131, 133,and 135. Field plates 141, 143, 145, 147, 149, and 151 are “floating”that is, they do not connect to the guard rings. The completed structureoften includes back metallization and surface passivation (both notshown) formed by conventional methods known in the art.

[0045]FIG. 9 is a simplified cross-sectional view of an alternativeembodiment 200 of a guard ring structure according to the presentinvention. This embodiment uses P type main junction regions and P typeguard rings formed onto an N− type epitaxial for illustrative purposesonly. But it will be recognized that such an embodiment may also beformed with use of N type main junction regions and guard rings, andothers. The embodiment includes an N− type layer 202 formed overlying aN+ type substrate 204. Preferably, the N− type layer is epitaxiallyformed overlying a neutron transmuted N+type substrate. Of course, theparticular thicknesses and dopant concentrations will depend upon theapplication.

[0046] P type guard ring regions 204, 206, 208, and others form onto theN− type layer 202. A dielectric layer and field plate layer are alsodefined. The dielectric layer includes dielectric regions 210, 212, andothers, and the field plate layer includes fixed plates 214 and 216.Floating field plates 218, 220, 222, 224, 226, and others are alsodefined by the field plate. The embodiment 200 also includes adielectric layer 230 formed overlying a top surface of this structure,which may also be the structure of FIG. 7. An additional group of fieldplates 232, 234, 236, 238, 240, and others may be formed overlying suchdielectric layer. Of course, the particular configuration used dependsupon the application.

[0047] The embodiment of FIG. 9 is fabricated with additional processsteps to the partially completed embodiment of FIG. 8. For example, adielectric layer may be formed overlying the top surface of FIG. 8embodiment. The dielectric layer includes dielectric materials such assilicon dioxide, silicon nitride, and others. Preferably, the dielectriclayer is an oxide. The thickness of such a layer ranges from about 0.7μm to about 2.0 μm, and preferably at about 1.0 μm.

[0048] A field plate layer made from materials such as polysilicon,metal, and others, is formed overlying the dielectric layer. The fieldplate layer is defined to form multiple field plates 232, 234, 236, 238,240, and others. The thickness of such a field plate ranges from about0.3μm to about 1.0 μm, and preferably at about 0.55 μm. Preferably, eachof the field plate regions is formed overlying an area between theunderlying polysilicon regions 214, 216, 218, 220, 222, 224, 226, andothers.

[0049] The multiple field plate layers of FIG. 9 further reduce theelectric field in the underlying semiconductor, and lessen fieldconcentration effects. Each of the field plates typically assumes avoltage potential between its surrounding guard rings. The configurationof multiple field plate layers provides for a more uniform distributionof electric fields in the semiconductor, thereby promoting highervoltage applications.

[0050] In a further alternative embodiment 300, a guard ring structureincludes multiple field plates that are allowed to “float” that is, theyare not in contact with a guard ring region as illustrated by FIG. 10.The embodiment 300 includes an N− type layer 303 formed overlying an N+type substrate 301. P type guard rings 304, 306, and 308 are defined inthe N+ type layer. A scribe line 310 may also be defined at a peripheralregion of the guard ring structure. Dielectric regions 312, 314, 316,and 318 are formed in regions between each of the P type guard rings.

[0051] The embodiment of FIG. 10 also includes multiple field plates,some of which float and others that do not float. A first field plate302, typically nearest to the main junction region 302, is connected tothe main junction region with use of a metal contact 340. A field plate326 is also connected to a last guard ring region 308. Another fieldplate 328 is connected to the scribe line with use of contact 345. Asfor the remaining field plates, they are allowed to “float,” that is,each is not connected to a guard ring. For example, field plates 322 and324 do not connect to guard rings 304 and 306, respectively.

[0052] The floating field plate design lessens field concentrationeffects by reducing the potential between each field plate and itsadjacent guard ring. For example, the potential between guard ring 306and field plate 322 is less than a corresponding structure of FIG. 1.The potential between guard ring 308 and field plate 324 is also lessthan a corresponding structure of FIG. 1, and so on. By way of thisstructure, the potential between a field plate and its guard ringreduces by about 5% or greater.

[0053] FIGS. 11 is a simplified top-view diagram of an embodiment of thepresent invention. The top-view includes several types of field platestructures, core region 430, contacts 434, 436, metallization 432, andother structures. The field plates illustrated include floating fieldplates 402, 404, 406, 408, 410, 412, and 414 (collectively defined asreference numeral 450) and field plates 418, 420, and 422 (collectivelydefined as reference numeral 460) located in an annular region. Anotherfield plate 416 connected to a guard ring region is also illustrated.Each of the floating field plates is not connected to an adjacent guardring region 401. However, field plate 416 connects to an adjacent guardring region 403 through contact 434, typically formed from metallizationlayer 434 and via structure 435. The other field plates 418, 420, and422 are also floating, but do not have guard ring structure located inbetween. Each of the field plates 418, 420, and 422 often form overlyinga dielectric layer 423 in the annular region. The combination of thefield plate structures provide reduced electric fields, and thereforehigher device breakdown voltages.

[0054]FIG. 2 is a simplified cross-sectional view of an alternativeembodiment 500 according to the present invention using multipledielectric layers. The embodiment includes P type guard rings 505, 507formed onto an N type substrate 503. A first dielectric layer 509 isdefined overlying each of the regions 515, 517 between the P type guardrings. A second dielectric layer 511 is defined overlying portions ofthe first dielectric layer. The combination of first and seconddielectric layers includes a thinner region 519 near the main junctionregion, away from the scribe region of the integrated circuit. Theembodiment includes an exposed first dielectric region near the mainjunction region to form a “step-like” structure. As previously noted,the dielectric layers can be formed from any suitable material such assilicon dioxide, silicon nitride, or the like, and combinations thereof.Field plates 513 are then defined overlying portions of the first andsecond dielectric layer.

[0055] The field plate portion overlying the first dielectric layer iscloser to region 515 than the field plate portion defined over both thefirst and second dielectric layers. The structure provides the desireddistribution of electric field on each of the field plates 513, therebyreducing the electric field in region 515. Any of previously mentionedembodiments may be modified by the structure of FIG. 12.

[0056] While the above is a full description of the specificembodiments, various modifications, alternative constructions, andequivalents may be used. For example, while the description above is interms of P type guard ring regions, it would be possible to implementthe present invention with a N type guard ring regions, or the like.Furthermore, while the embodiments shown are generally in terms of anMOSFET, thyristor, and IGBT, it would be possible to implement theimproved substrate in the present invention with any device such as, forexample, an MCT, or the like.

[0057] Therefore, the above description and illustrations should not betaken as limiting the scope of the present invention which is defined bythe appended claims.

What is claimed is:
 1. A power device comprising: a semiconductorsubstrate comprising a top surface with an active region, a guard ringregion, and a peripheral region, said active region including a junctionregion; a plurality of guard rings formed onto said semiconductorsubstrate in said guard ring region, said guard ring region beingbetween said active region and said peripheral region, said plurality ofguard rings comprising a first guard ring nearest to said junctionregion and a last guard ring nearest to said peripheral region; adielectric layer overlying said top surface and having portions betweeneach of said plurality of guard rings, said dielectric layer having aportion between said junction region and said first guard ring, saiddielectric layer having a portion between said last guard ring and saidperipheral region; and a field plate layer, said field plate layeroverlying each of said dielectric layer portions between each of saidplurality of guard rings, said field plate layer overlying saiddielectric layer portion between said junction region and said firstguard ring, and said field plate layer overlying said dielectric layerportion between said last guard ring and said peripheral region.
 2. Thedevice of claim 1 further comprising a contact layer formed overlying aportion of said junction region and a portion of said field plate layerformed overlying said dielectric layer portion between said junctionregion and said first guard ring.
 3. The device of claim 1 furthercomprising a contact layer formed overlying a portion said last guardring and a portion of said field plate layer overlying said dielectriclayer portion between said last guard ring and said peripheral region.4. The device of claim 1 further comprising an insulating layeroverlying said guard rings and field plate layer.
 5. The device of claim1 wherein each of said guard rings are substantially parallel to eachother.
 6. The device of claim 1 wherein said field plate layer comprisespolysilicon.
 7. The device of claim 1 wherein each of said guard ringscomprise P type/P+ type diffusions.
 8. The device of claim 7 whereinsaid P type impurity is at a concentration ranging from about 10¹⁴atoms/μm³ to about 10¹⁸ atoms/μm³, and said P+ type impurity is at aconcentration ranging from about 10¹⁵ atoms/μm³ to about 10¹⁵ atoms/μm³.9. The device of claim 1 wherein said peripheral region includes ascribe region.
 10. The device of claim 1 wherein said semiconductorsubstrate comprises an N+ type layer and an N− type layer overlying saidN+ type layer.
 11. The device of claim 1 wherein said field plate layeroverlying said dielectric layer portion between said last ground ringand said peripheral region comprise a plurality of field plates, saidplurality of field plates comprising a first field plate and a secondfield plate, said first field plate being separated from said secondfield plate.
 12. The device of claim 11 further comprising a firstcontact formed overlying a portion said last guard ring and a portion ofsaid first field plate and a second contact layer formed overlying aportion of said peripheral region and said second field plate.
 13. Thedevice of claim 12 wherein said plurality of field plates furthercomprises at least one field plate between said first field plate andsaid second field plate, said at least one field plate being separatedfrom said first field plate and said second field plate.
 14. The deviceof claim 13 further comprising a dielectric layer separating said atleast one field plate from said first field plate and said second fieldplate.
 15. The device of claim 14 wherein said dielectric layer includesa thickness ranging from about 0.05 μm to about 2.5 μm.
 16. The deviceof claim 1 wherein said field plate layer overlying each of saiddielectric layer portions between each of said plurality of guard ringscomprises a plurality of field plates, said plurality of field platesbeing separated from each other.
 17. A power device comprising: asemiconductor substrate comprising a top surface with an active region,a guard ring region, and a peripheral region, said active regionincluding a junction region; a plurality of guard rings formed onto saidsemiconductor substrate in said guard ring region, said guard ringregion being between said active region and said peripheral region, saidplurality of guard rings comprising a first guard ring nearest to saidjunction region and a last guard ring nearest to said peripheral region;a dielectric layer overlying said top surface and having portionsbetween each of said plurality of guard rings, said dielectric layerhaving a portion between said junction region and said first guard ring,said dielectric layer having a portion between said last guard ring andsaid peripheral region; and a field plate layer, said field plate layercomprising a plurality of field plates overlying each of said dielectriclayer portions between each of said plurality of guard rings, said fieldplate layer overlying said dielectric layer portion between saidjunction region and said first guard ring, and said field plate layercomprising a plurality of field plates overlying said dielectric layerportion between said last guard ring and said peripheral region.
 18. Thedevice of claim 17 wherein at least one of said field plates overlyingeach of said dielectric layer portions between each of said plurality ofguard rings is coupled to one of said plurality of guard rings.
 19. Thedevice of claim 17 wherein said field plate layer overlying saiddielectric layer portion between said junction region and said firstguard ring is coupled to said junction region.
 20. The device of claim17 wherein at least one of said plurality of field plates overlying saiddielectric layer portion between said last guard ring and saidperipheral region is coupled to said last guard ring.
 21. The device ofclaim 17 wherein at least one of said plurality of field platesoverlying said dielectric layer portion between said last guard ring andsaid peripheral region is coupled to said peripheral region.
 22. Thedevice of claim 17 wherein said peripheral region is a scribe region.23. The device of claim 17 wherein said plurality of field platesoverlying said dielectric layer portion between said last guard ring andsaid peripheral region is separated from each other by a distance lessthan about 4 μm.
 24. The device of claim 17 wherein a plurality of saidfield plates overlying each of said dielectric layer portions betweeneach of said plurality of guard rings is separated from each other by adistance less than about 4 μm.
 25. A method of forming a guard ringstructure comprising the steps of: providing a partially completedsemiconductor device with an active region, guard ring region, andperipheral region, said active region including a junction region, saidguard ring region being between said active region and said peripheralregion, and said guard ring region including a plurality of diffusionregions; forming a dielectric layer overlying said partially completedsemiconductor substrate; forming a field plate layer overlying saiddielectric layer; defining said dielectric layer and field plate layerto form a plurality of openings over said diffusion regions, saiddielectric layer and field plate layer being defined to expose saidjunction region and said peripheral region; and providing implants intosaid openings to define a plurality of guard rings, said plurality ofguard rings including a first guard ring proximate to said junctionregion and a last guard ring proximate to said peripheral region. 26.The method of claim 25 wherein said field plate layer comprises aplurality of field plates between each of said openings, said pluralityof field plates being separated from each other.
 27. The method of claim25 wherein said field plate layer comprises a plurality of field platesbetween said last guard ring and said peripheral region, said pluralityof field plates being separated from each other.
 28. The method of claim27 further comprising a step of forming metallization overlying saidperipheral region and at least one of said field plates between saidlast guard ring and said peripheral region.
 29. The method of claim 28wherein said step of forming metallization forms metallization overlyingsaid last guard ring and at least one of said plurality of field platesbetween said last guard ring and said peripheral region.
 30. The methodof claim 29 wherein said step of forming metallization formsmetallization overlying said junction region and a portion of said fieldplate layer adjacent to said exposed junction region.
 31. The method ofclaim 25 wherein said dielectric layer comprises multiple dielectriclayers.
 32. The method of claim 31 wherein said multiple dielectriclayers comprise a first dielectric layer formed overlying a portion ofsaid second dielectric layer.
 33. The method of claim 32 wherein saidstep of forming a field plate layer comprises forming said field platelayer over a portion of said first dielectric layer and a portion ofsaid second dielectric layer.